The present invention relates to the field of image sensors and more particularly, CMOS-type area image sensors., and imaging reading, transmission and/or reproducing apparatus such as facsimile devices, document copiers, and optical barcode readers.
Presently many imaging systems use solid-state charge coupled devices (CCD) as image sensors which sense input light, convert light intensity into electronic signal for readout. Because CCDs are made by highly specialized fabrication processes designed for imaging purposes, CCD fabrication processes are generally not compatible with a complementary-metal-oxide-silicon (xe2x80x9cCMOSxe2x80x9d) device fabrication process. Today almost all microprocessors, application-specific integrated circuits (ASICs), and memory products are CMOS-type devices. As a result, a CCD image sensor requires separate support electronics, usually CMOS devices, to provide timing, clocking and signal processing functions. Another drawback of CCDs is that they consume a large amount of power (e.g., watts). In addition, high spatial resolution area CCD sensors are expensive.
CMOS as a silicon technology has also been used to perform image sensing. The purported advantage of CMOS image sensors is the potential of integrating image sensing, readout, analog to digital conversion (ADC), signal processing, control and memory, all on a single chip. This results in a much smaller and lower cost imaging system, and it consumes a lot less power than a CCD imaging system.
However, earlier generations of CMOS have large minimum transistor gate-length (e.g., greater than 2 microns). Such large transistor size would make a CMOS image sensor pixel too big for required spatial resolution in typical image sensing applications. The spatial resolution of an image sensor refers to the planar size of an image sensor array (e.g., a 640xc3x97480 is of VGA spatial resolution).
With the recent improvement of the CMOS technology, the transistor size of each generation CMOS device rapidly shrinks, following an exponential trend commonly called as the Moore""s law. At around 1.2 micron feature size, CMOS technology has become competitive in making image sensors, at least for low spatial resolution consumer grade applications.
The continued advancement of the CMOS technology, however, presents a new challenge for CMOS image sensors. As the minimum feature size of a CMOS shrinks (e.g., from 0.5 micron to 0.35, 0.25, 0.18, 0.13 micron), voltage supply used for CMOS devices reduces, junction depth decreases, and doping level increases. This generally leads to a smaller signal swing, reduced photo detector sensitivity and increased leakage current. As a result, the signal-to-noise ratio (SNR) and the dynamic range of a CMOS image sensor is likely to get worse, resulting in degraded image quality. Consequently, as the minimum feature size of a CMOS process continues to shrink, it would be very difficult to provide a high bit resolution CMOS area image sensor. High bit resolution refers herein to the brightness resolution and is fundamentally limited by the signal-to-noise ratio.
It has been proposed that some kind of modification of a standard CMOS process (i.e., making changes to the CMOS fabrication process designed for making digital and/or analog circuits for the specific purpose of making an image sensor) be made in order to achieve adequate imaging performance in CMOS image sensors. Such modification may include, for example, an additional step of ion implantation, that is intended for improving the image sensing of photo detectors in the CMOS sensors.
The drawback of modifying a standard CMOS process is that it detracts from the fundamental advantage of making image sensors by using the same CMOS process for making analog or digital circuit to make CMOS image sensors, i.e., the economy of fabricating them on standard CMOS fabrication lines.
Fossum, E., in xe2x80x9cCMOS Image Sensors: Electronic Camera On A Chipxe2x80x9d, IEDM 95, 17-25, 1995, described a 256xc3x97256 CMOS image sensor made using 0.9 micron CMOS technologies, and 1024xc3x971024 image sensors made using 0.5 micron CMOS technologies, both without monolithically integrated timing and control circuit. This type of CMOS image sensors without integrated timing and control circuit are not desirable because of the lack of integration. The article also discloses a 256xc3x97256 CMOS image sensor with integrated timing and control logic made with 1.2 micron process. The spatial resolution of this chip, however, is too low for high spatial resolution applications, such as facsimile. Further, if scaled to the deep sub-micron range, the image quality obtained from this image sensor would be degraded due to reduced signal level.
U.S. Pat. No. 5,666,159 describes a CCD video camera integrated in a cellular telephone handset. However, due to the drawbacks associated with CCD, this integrated CCD camera/cellular phone would consume a large amount of power and not suitable for cellular application.
It is therefore an object of the present invention to provide a high spatial resolution CMOS image sensor having a minimum feature size which can be continuously scaled as CMOS technologies advances;
It is another object of the present invention to provide a CMOS area image sensor which can be used for both document imaging and video imaging;
It is another object of the present invention to provide a CMOS area image sensor for document imaging, such as facsimile imaging;
It is a further object of the present invention to apply the CMOS area image sensors of the present invention in image sensing applications; and
It is a still further object of the present invention to provide a CMOS area image sensor for portable document-related image applications.
These and other objects are achieved in the present invention, which provides a CMOS area image sensor having a bit resolution of less than 6-bits and a high spatial resolution. The CMOS sensor is fabricated in accordance with a CMOS process characterized by having a minimum gate length of 0.35 micron or less. The CMOS image sensor includes a pixel sensor array having at least 1000xc3x97900 pixels and a timing and control generation circuit for generating timing and control signals for said image sensor. A row selecting circuit is provided for selecting one or more rows of pixels for readout. A column processor is provided for selecting one of more columns of pixels for readout. An input/output circuit is provided as a data interface for the CMOS area image sensor. The timing and control generation circuit, the row selecting circuit, the column processor, and input/output circuit are monolithically integrated with the pixel sensor array.
Preferably, the CMOS area image sensor further includes a monolithically integrated digital signal processor for performing digital signal processing. More preferably, for facsimile applications, the digital signal processor includes signal processing means for facsimile application; for document reproduction or copying, the digital signal processor includes signal processing means for document reproduction or copying; for barcode reading and decoding, the digital signal processor includes signal processing means for barcode sensing and decoding. A monolithically integrated memory device may also be included in the CMOS area image sensor.
In accordance with another aspect of the present invention, a CMOS area image sensor with analog dithering is provided. The CMOS area image sensor includes analog dithering means for performing dithering on analog image signal before or during such analog signal being converted to digital image signal, but not after such signal is digitized.
In accordance with another aspect of the present invention, a variable bit and spatial resolution CMOS area image sensor is provided. This CMOS sensor includes means for performing suitable spatial oversampling to achieve desired bit resolution. This CMOS sensor may be used for document imaging, such as facsimile imaging and copying where low bit resolution is sufficient, as well as video imaging or photography where high bit resolution is required.
In accordance with another aspect of the present invention, an imaging apparatus is provided. The apparatus includes an optical system for projecting an image onto a CMOS area image sensor of the present invention. The CMOS image sensor has a bit resolution of less than 6-bits and a high spatial resolution and is fabricated in accordance with a CMOS process characterized by having a minimum gate length of 0.35 micron or less. The CMOS image sensor includes a pixel sensor array having at least 1000xc3x97900 pixels, a timing and control generation circuit for generating timing and control signals for said image sensor, a row selecting circuit for selecting one or more rows of pixels for readout, a column processor for selecting one of more columns of pixels for readout, and an input/output circuit for providing a data interface.
In accordance with another aspect of the present invention, a communications device for cellular voice communications and image transmission is provided. The device includes cellular communications means for providing cellular communications, a CMOS area image sensor of the present invention for facsimile operation, and means for transmitting facsimile image data representing an image captured by the CMOS image sensor to a remote location.